1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
|
/**********************************************************************
*
* Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful but, except
* as otherwise stated in writing, without any warranty; without even the
* implied warranty of merchantability or fitness for a particular purpose.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Contact Information:
* Imagination Technologies Ltd. <gpl-support@imgtec.com>
* Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
*
******************************************************************************/
#if !defined (__SGXINFO_H__)
#define __SGXINFO_H__
#include "sgxscript.h"
#include "servicesint.h"
#include "services.h"
#include "sgxapi_km.h"
#include "sgx_mkif_km.h"
#define SGX_MAX_DEV_DATA 24
#define SGX_MAX_INIT_MEM_HANDLES 16
typedef struct _SGX_BRIDGE_INFO_FOR_SRVINIT
{
IMG_DEV_PHYADDR sPDDevPAddr;
PVRSRV_HEAP_INFO asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
} SGX_BRIDGE_INFO_FOR_SRVINIT;
typedef enum _SGXMKIF_CMD_TYPE_
{
SGXMKIF_CMD_TA = 0,
SGXMKIF_CMD_TRANSFER = 1,
SGXMKIF_CMD_2D = 2,
SGXMKIF_CMD_POWER = 3,
SGXMKIF_CMD_CLEANUP = 4,
SGXMKIF_CMD_GETMISCINFO = 5,
SGXMKIF_CMD_PROCESS_QUEUES = 6,
SGXMKIF_CMD_MAX = 7,
SGXMKIF_CMD_FORCE_I32 = -1,
} SGXMKIF_CMD_TYPE;
typedef struct _SGX_BRIDGE_INIT_INFO_
{
IMG_HANDLE hKernelCCBMemInfo;
IMG_HANDLE hKernelCCBCtlMemInfo;
IMG_HANDLE hKernelCCBEventKickerMemInfo;
IMG_HANDLE hKernelSGXHostCtlMemInfo;
IMG_HANDLE hKernelSGXTA3DCtlMemInfo;
IMG_HANDLE hKernelSGXMiscMemInfo;
IMG_UINT32 aui32HostKickAddr[SGXMKIF_CMD_MAX];
SGX_INIT_SCRIPTS sScripts;
IMG_UINT32 ui32ClientBuildOptions;
SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
#if defined(SGX_SUPPORT_HWPROFILING)
IMG_HANDLE hKernelHWProfilingMemInfo;
#endif
#if defined(SUPPORT_SGX_HWPERF)
IMG_HANDLE hKernelHWPerfCBMemInfo;
#endif
#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
IMG_HANDLE hKernelEDMStatusBufferMemInfo;
#endif
#if defined(SGX_FEATURE_OVERLAPPED_SPM)
IMG_HANDLE hKernelTmpRgnHeaderMemInfo;
#endif
#if defined(SGX_FEATURE_SPM_MODE_0)
IMG_HANDLE hKernelTmpDPMStateMemInfo;
#endif
IMG_UINT32 ui32EDMTaskReg0;
IMG_UINT32 ui32EDMTaskReg1;
IMG_UINT32 ui32ClkGateStatusReg;
IMG_UINT32 ui32ClkGateStatusMask;
#if defined(SGX_FEATURE_MP)
IMG_UINT32 ui32MasterClkGateStatusReg;
IMG_UINT32 ui32MasterClkGateStatusMask;
#endif
IMG_UINT32 ui32CacheControl;
IMG_UINT32 asInitDevData[SGX_MAX_DEV_DATA];
IMG_HANDLE asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
} SGX_BRIDGE_INIT_INFO;
typedef struct _SGX_DEVICE_SYNC_LIST_
{
PSGXMKIF_HWDEVICE_SYNC_LIST psHWDeviceSyncList;
IMG_HANDLE hKernelHWSyncListMemInfo;
PVRSRV_CLIENT_MEM_INFO *psHWDeviceSyncListClientMemInfo;
PVRSRV_CLIENT_MEM_INFO *psAccessResourceClientMemInfo;
volatile IMG_UINT32 *pui32Lock;
struct _SGX_DEVICE_SYNC_LIST_ *psNext;
IMG_UINT32 ui32NumSyncObjects;
IMG_HANDLE ahSyncHandles[1];
} SGX_DEVICE_SYNC_LIST, *PSGX_DEVICE_SYNC_LIST;
typedef struct _SGX_INTERNEL_STATUS_UPDATE_
{
CTL_STATUS sCtlStatus;
IMG_HANDLE hKernelMemInfo;
IMG_UINT32 ui32LastStatusUpdateDumpVal;
} SGX_INTERNEL_STATUS_UPDATE;
typedef struct _SGX_CCB_KICK_
{
SGXMKIF_COMMAND sCommand;
IMG_HANDLE hCCBKernelMemInfo;
IMG_UINT32 ui32NumDstSyncObjects;
IMG_HANDLE hKernelHWSyncListMemInfo;
IMG_HANDLE *pahDstSyncHandles;
IMG_UINT32 ui32NumTAStatusVals;
IMG_UINT32 ui32Num3DStatusVals;
#if defined(SUPPORT_SGX_NEW_STATUS_VALS)
SGX_INTERNEL_STATUS_UPDATE asTAStatusUpdate[SGX_MAX_TA_STATUS_VALS];
SGX_INTERNEL_STATUS_UPDATE as3DStatusUpdate[SGX_MAX_3D_STATUS_VALS];
#else
IMG_HANDLE ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
IMG_HANDLE ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
#endif
IMG_BOOL bFirstKickOrResume;
#if (defined(NO_HARDWARE) || defined(PDUMP))
IMG_BOOL bTerminateOrAbort;
#endif
#if defined(SUPPORT_SGX_HWPERF)
IMG_BOOL bKickRender;
#endif
IMG_UINT32 ui32CCBOffset;
#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
IMG_UINT32 ui32NumTASrcSyncs;
IMG_HANDLE ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS];
IMG_UINT32 ui32NumTADstSyncs;
IMG_HANDLE ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS];
IMG_UINT32 ui32Num3DSrcSyncs;
IMG_HANDLE ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS];
#else
IMG_UINT32 ui32NumSrcSyncs;
IMG_HANDLE ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
#endif
IMG_BOOL bTADependency;
IMG_HANDLE hTA3DSyncInfo;
IMG_HANDLE hTASyncInfo;
IMG_HANDLE h3DSyncInfo;
#if defined(PDUMP)
IMG_UINT32 ui32CCBDumpWOff;
#endif
#if defined(NO_HARDWARE)
IMG_UINT32 ui32WriteOpsPendingVal;
#endif
} SGX_CCB_KICK;
#define SGX_KERNEL_USE_CODE_BASE_INDEX 15
typedef struct _SGX_CLIENT_INFO_
{
IMG_UINT32 ui32ProcessID;
IMG_VOID *pvProcess;
PVRSRV_MISC_INFO sMiscInfo;
IMG_UINT32 asDevData[SGX_MAX_DEV_DATA];
} SGX_CLIENT_INFO;
typedef struct _SGX_INTERNAL_DEVINFO_
{
IMG_UINT32 ui32Flags;
IMG_HANDLE hHostCtlKernelMemInfoHandle;
IMG_BOOL bForcePTOff;
} SGX_INTERNAL_DEVINFO;
#if defined(TRANSFER_QUEUE)
typedef struct _PVRSRV_TRANSFER_SGX_KICK_
{
IMG_HANDLE hCCBMemInfo;
IMG_UINT32 ui32SharedCmdCCBOffset;
IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
IMG_HANDLE hTASyncInfo;
IMG_HANDLE h3DSyncInfo;
IMG_UINT32 ui32NumSrcSync;
IMG_HANDLE ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
IMG_UINT32 ui32NumDstSync;
IMG_HANDLE ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
IMG_UINT32 ui32Flags;
IMG_UINT32 ui32PDumpFlags;
#if defined(PDUMP)
IMG_UINT32 ui32CCBDumpWOff;
#endif
} PVRSRV_TRANSFER_SGX_KICK, *PPVRSRV_TRANSFER_SGX_KICK;
#if defined(SGX_FEATURE_2D_HARDWARE)
typedef struct _PVRSRV_2D_SGX_KICK_
{
IMG_HANDLE hCCBMemInfo;
IMG_UINT32 ui32SharedCmdCCBOffset;
IMG_DEV_VIRTADDR sHW2DContextDevVAddr;
IMG_UINT32 ui32NumSrcSync;
IMG_HANDLE ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS];
IMG_HANDLE hDstSyncInfo;
IMG_HANDLE hTASyncInfo;
IMG_HANDLE h3DSyncInfo;
IMG_UINT32 ui32PDumpFlags;
#if defined(PDUMP)
IMG_UINT32 ui32CCBDumpWOff;
#endif
} PVRSRV_2D_SGX_KICK, *PPVRSRV_2D_SGX_KICK;
#endif
#endif
#define PVRSRV_SGX_DIFF_NUM_COUNTERS 9
typedef struct _PVRSRV_SGXDEV_DIFF_INFO_
{
IMG_UINT32 aui32Counters[PVRSRV_SGX_DIFF_NUM_COUNTERS];
IMG_UINT32 ui32Time[3];
IMG_UINT32 ui32Marker[2];
} PVRSRV_SGXDEV_DIFF_INFO, *PPVRSRV_SGXDEV_DIFF_INFO;
#endif
|
