1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
|
/**********************************************************************
*
* Copyright (C) Imagination Technologies Ltd. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful but, except
* as otherwise stated in writing, without any warranty; without even the
* implied warranty of merchantability or fitness for a particular purpose.
* See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Contact Information:
* Imagination Technologies Ltd. <gpl-support@imgtec.com>
* Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
*
******************************************************************************/
#if !defined (__SGX_MKIF_KM_H__)
#define __SGX_MKIF_KM_H__
#include "img_types.h"
#include "servicesint.h"
#include "sgxapi_km.h"
#if !defined (SGX_MP_CORE_SELECT)
#if defined(SGX_FEATURE_MP)
#define SGX_REG_BANK_SHIFT (14)
#define SGX_REG_BANK_SIZE (1 << SGX_REG_BANK_SHIFT)
#define SGX_REG_BANK_BASE_INDEX (2)
#define SGX_REG_BANK_MASTER_INDEX (1)
#define SGX_MP_CORE_SELECT(x,i) (x + ((i + SGX_REG_BANK_BASE_INDEX) * SGX_REG_BANK_SIZE))
#define SGX_MP_MASTER_SELECT(x) (x + (SGX_REG_BANK_MASTER_INDEX * SGX_REG_BANK_SIZE))
#else
#define SGX_MP_CORE_SELECT(x,i) (x)
#endif
#endif
typedef struct _SGXMKIF_COMMAND_
{
IMG_UINT32 ui32ServiceAddress;
IMG_UINT32 ui32CacheControl;
IMG_UINT32 ui32Data[6];
} SGXMKIF_COMMAND;
typedef struct _PVRSRV_SGX_KERNEL_CCB_
{
SGXMKIF_COMMAND asCommands[256];
} PVRSRV_SGX_KERNEL_CCB;
typedef struct _PVRSRV_SGX_CCB_CTL_
{
IMG_UINT32 ui32WriteOffset;
IMG_UINT32 ui32ReadOffset;
} PVRSRV_SGX_CCB_CTL;
typedef struct _SGXMKIF_HOST_CTL_
{
#if defined(PVRSRV_USSE_EDM_BREAKPOINTS)
IMG_UINT32 ui32BreakpointDisable;
IMG_UINT32 ui32Continue;
#endif
volatile IMG_UINT32 ui32InitStatus;
volatile IMG_UINT32 ui32PowerStatus;
volatile IMG_UINT32 ui32CleanupStatus;
#if defined(FIX_HW_BRN_28889)
volatile IMG_UINT32 ui32InvalStatus;
#endif
#if defined(SUPPORT_HW_RECOVERY)
IMG_UINT32 ui32uKernelDetectedLockups;
IMG_UINT32 ui32HostDetectedLockups;
IMG_UINT32 ui32HWRecoverySampleRate;
#endif
IMG_UINT32 ui32uKernelTimerClock;
IMG_UINT32 ui32ActivePowManSampleRate;
IMG_UINT32 ui32InterruptFlags;
IMG_UINT32 ui32InterruptClearFlags;
IMG_UINT32 ui32BPSetClearSignal;
IMG_UINT32 ui32NumActivePowerEvents;
IMG_UINT32 ui32TimeWraps;
IMG_UINT32 ui32HostClock;
IMG_UINT32 ui32AssertFail;
#if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS)
IMG_UINT32 aui32PerfGroup[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
IMG_UINT32 aui32PerfBit[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
#else
IMG_UINT32 ui32PerfGroup;
#endif
#if defined(FIX_HW_BRN_31939)
IMG_UINT32 ui32BRN31939Mem;
#endif
IMG_UINT32 ui32OpenCLDelayCount;
} SGXMKIF_HOST_CTL;
#define SGXMKIF_CMDTA_CTRLFLAGS_READY 0x00000001
typedef struct _SGXMKIF_CMDTA_SHARED_
{
IMG_UINT32 ui32CtrlFlags;
IMG_UINT32 ui32NumTAStatusVals;
IMG_UINT32 ui32Num3DStatusVals;
IMG_UINT32 ui32TATQSyncWriteOpsPendingVal;
IMG_DEV_VIRTADDR sTATQSyncWriteOpsCompleteDevVAddr;
IMG_UINT32 ui32TATQSyncReadOpsPendingVal;
IMG_DEV_VIRTADDR sTATQSyncReadOpsCompleteDevVAddr;
IMG_UINT32 ui323DTQSyncWriteOpsPendingVal;
IMG_DEV_VIRTADDR s3DTQSyncWriteOpsCompleteDevVAddr;
IMG_UINT32 ui323DTQSyncReadOpsPendingVal;
IMG_DEV_VIRTADDR s3DTQSyncReadOpsCompleteDevVAddr;
#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
IMG_UINT32 ui32NumTASrcSyncs;
PVRSRV_DEVICE_SYNC_OBJECT asTASrcSyncs[SGX_MAX_TA_SRC_SYNCS];
IMG_UINT32 ui32NumTADstSyncs;
PVRSRV_DEVICE_SYNC_OBJECT asTADstSyncs[SGX_MAX_TA_DST_SYNCS];
IMG_UINT32 ui32Num3DSrcSyncs;
PVRSRV_DEVICE_SYNC_OBJECT as3DSrcSyncs[SGX_MAX_3D_SRC_SYNCS];
#else
IMG_UINT32 ui32NumSrcSyncs;
PVRSRV_DEVICE_SYNC_OBJECT asSrcSyncs[SGX_MAX_SRC_SYNCS];
#endif
PVRSRV_DEVICE_SYNC_OBJECT sTA3DDependency;
CTL_STATUS sCtlTAStatusInfo[SGX_MAX_TA_STATUS_VALS];
CTL_STATUS sCtl3DStatusInfo[SGX_MAX_3D_STATUS_VALS];
} SGXMKIF_CMDTA_SHARED;
#define SGXTQ_MAX_STATUS SGX_MAX_TRANSFER_STATUS_VALS + 2
#define SGXMKIF_TQFLAGS_NOSYNCUPDATE 0x00000001
#define SGXMKIF_TQFLAGS_KEEPPENDING 0x00000002
#define SGXMKIF_TQFLAGS_TATQ_SYNC 0x00000004
#define SGXMKIF_TQFLAGS_3DTQ_SYNC 0x00000008
#if defined(SGX_FEATURE_FAST_RENDER_CONTEXT_SWITCH)
#define SGXMKIF_TQFLAGS_CTXSWITCH 0x00000010
#endif
#define SGXMKIF_TQFLAGS_DUMMYTRANSFER 0x00000020
typedef struct _SGXMKIF_TRANSFERCMD_SHARED_
{
IMG_UINT32 ui32NumSrcSyncs;
PVRSRV_DEVICE_SYNC_OBJECT asSrcSyncs[SGX_MAX_SRC_SYNCS];
IMG_UINT32 ui32NumDstSyncs;
PVRSRV_DEVICE_SYNC_OBJECT asDstSyncs[SGX_MAX_DST_SYNCS];
IMG_UINT32 ui32TASyncWriteOpsPendingVal;
IMG_DEV_VIRTADDR sTASyncWriteOpsCompleteDevVAddr;
IMG_UINT32 ui32TASyncReadOpsPendingVal;
IMG_DEV_VIRTADDR sTASyncReadOpsCompleteDevVAddr;
IMG_UINT32 ui323DSyncWriteOpsPendingVal;
IMG_DEV_VIRTADDR s3DSyncWriteOpsCompleteDevVAddr;
IMG_UINT32 ui323DSyncReadOpsPendingVal;
IMG_DEV_VIRTADDR s3DSyncReadOpsCompleteDevVAddr;
IMG_UINT32 ui32NumStatusVals;
CTL_STATUS sCtlStatusInfo[SGXTQ_MAX_STATUS];
} SGXMKIF_TRANSFERCMD_SHARED, *PSGXMKIF_TRANSFERCMD_SHARED;
#if defined(SGX_FEATURE_2D_HARDWARE)
typedef struct _SGXMKIF_2DCMD_SHARED_ {
IMG_UINT32 ui32NumSrcSync;
PVRSRV_DEVICE_SYNC_OBJECT sSrcSyncData[SGX_MAX_2D_SRC_SYNC_OPS];
PVRSRV_DEVICE_SYNC_OBJECT sDstSyncData;
PVRSRV_DEVICE_SYNC_OBJECT sTASyncData;
PVRSRV_DEVICE_SYNC_OBJECT s3DSyncData;
} SGXMKIF_2DCMD_SHARED, *PSGXMKIF_2DCMD_SHARED;
#endif
typedef struct _SGXMKIF_HWDEVICE_SYNC_LIST_
{
IMG_DEV_VIRTADDR sAccessDevAddr;
IMG_UINT32 ui32NumSyncObjects;
PVRSRV_DEVICE_SYNC_OBJECT asSyncData[1];
} SGXMKIF_HWDEVICE_SYNC_LIST, *PSGXMKIF_HWDEVICE_SYNC_LIST;
#define PVRSRV_USSE_EDM_INIT_COMPLETE (1UL << 0)
#define PVRSRV_USSE_EDM_POWMAN_IDLE_COMPLETE (1UL << 2)
#define PVRSRV_USSE_EDM_POWMAN_POWEROFF_COMPLETE (1UL << 3)
#define PVRSRV_USSE_EDM_POWMAN_POWEROFF_RESTART_IMMEDIATE (1UL << 4)
#define PVRSRV_USSE_EDM_POWMAN_NO_WORK (1UL << 5)
#define PVRSRV_USSE_EDM_INTERRUPT_HWR (1UL << 0)
#define PVRSRV_USSE_EDM_INTERRUPT_ACTIVE_POWER (1UL << 1)
#define PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE (1UL << 0)
#if defined(FIX_HW_BRN_28889)
#define PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE (1UL << 0)
#endif
#define PVRSRV_USSE_MISCINFO_READY 0x1UL
#define PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES 0x2UL
#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
#define PVRSRV_USSE_MISCINFO_MEMREAD 0x4UL
#define PVRSRV_USSE_MISCINFO_MEMWRITE 0x8UL
#if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
#define PVRSRV_USSE_MISCINFO_MEMREAD_FAIL 0x1UL << 31
#endif
#endif
#define PVRSRV_CLEANUPCMD_RT 0x1U
#define PVRSRV_CLEANUPCMD_RC 0x2U
#define PVRSRV_CLEANUPCMD_TC 0x3U
#define PVRSRV_CLEANUPCMD_2DC 0x4U
#define PVRSRV_CLEANUPCMD_PB 0x5U
#define PVRSRV_POWERCMD_POWEROFF 0x1U
#define PVRSRV_POWERCMD_IDLE 0x2U
#define PVRSRV_POWERCMD_RESUME 0x3U
#define PVRSRV_CTXSUSPCMD_SUSPEND 0x1U
#define PVRSRV_CTXSUSPCMD_RESUME 0x2U
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
#define SGX_BIF_DIR_LIST_INDEX_EDM (SGX_FEATURE_BIF_NUM_DIRLISTS - 1)
#else
#define SGX_BIF_DIR_LIST_INDEX_EDM (0)
#endif
#define SGXMKIF_CC_INVAL_BIF_PT 0x1
#define SGXMKIF_CC_INVAL_BIF_PD 0x2
#define SGXMKIF_CC_INVAL_BIF_SL 0x4
#define SGXMKIF_CC_INVAL_DATA 0x8
typedef struct _SGX_MISCINFO_STRUCT_SIZES_
{
#if defined (SGX_FEATURE_2D_HARDWARE)
IMG_UINT32 ui32Sizeof_2DCMD;
IMG_UINT32 ui32Sizeof_2DCMD_SHARED;
#endif
IMG_UINT32 ui32Sizeof_CMDTA;
IMG_UINT32 ui32Sizeof_CMDTA_SHARED;
IMG_UINT32 ui32Sizeof_TRANSFERCMD;
IMG_UINT32 ui32Sizeof_TRANSFERCMD_SHARED;
IMG_UINT32 ui32Sizeof_3DREGISTERS;
IMG_UINT32 ui32Sizeof_HWPBDESC;
IMG_UINT32 ui32Sizeof_HWRENDERCONTEXT;
IMG_UINT32 ui32Sizeof_HWRENDERDETAILS;
IMG_UINT32 ui32Sizeof_HWRTDATA;
IMG_UINT32 ui32Sizeof_HWRTDATASET;
IMG_UINT32 ui32Sizeof_HWTRANSFERCONTEXT;
IMG_UINT32 ui32Sizeof_HOST_CTL;
IMG_UINT32 ui32Sizeof_COMMAND;
} SGX_MISCINFO_STRUCT_SIZES;
#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
typedef struct _PVRSRV_SGX_MISCINFO_MEMACCESS
{
IMG_DEV_VIRTADDR sDevVAddr;
IMG_DEV_PHYADDR sPDDevPAddr;
} PVRSRV_SGX_MISCINFO_MEMACCESS;
#endif
typedef struct _PVRSRV_SGX_MISCINFO_INFO
{
IMG_UINT32 ui32MiscInfoFlags;
PVRSRV_SGX_MISCINFO_FEATURES sSGXFeatures;
SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
PVRSRV_SGX_MISCINFO_MEMACCESS sSGXMemAccessSrc;
PVRSRV_SGX_MISCINFO_MEMACCESS sSGXMemAccessDest;
#endif
} PVRSRV_SGX_MISCINFO_INFO;
#ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
#define SGXMK_TRACE_BUFFER_SIZE 512
#endif
#define SGXMKIF_HWPERF_CB_SIZE 0x100
typedef struct _SGXMKIF_HWPERF_CB_ENTRY_
{
IMG_UINT32 ui32FrameNo;
IMG_UINT32 ui32PID;
IMG_UINT32 ui32RTData;
IMG_UINT32 ui32Type;
IMG_UINT32 ui32Ordinal;
IMG_UINT32 ui32Info;
IMG_UINT32 ui32TimeWraps;
IMG_UINT32 ui32Time;
IMG_UINT32 ui32Counters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_COUNTERS];
IMG_UINT32 ui32MiscCounters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS];
} SGXMKIF_HWPERF_CB_ENTRY;
typedef struct _SGXMKIF_HWPERF_CB_
{
IMG_UINT32 ui32Woff;
IMG_UINT32 ui32Roff;
IMG_UINT32 ui32Ordinal;
SGXMKIF_HWPERF_CB_ENTRY psHWPerfCBData[SGXMKIF_HWPERF_CB_SIZE];
} SGXMKIF_HWPERF_CB;
#endif
|
