Age | Commit message (Collapse) | Author |
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Manikanta Sreeram <manikanta.sreeram@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Manikanta Sreeram <manikanta.sreeram@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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axi_ethernet.tcl: Fix the issue when dclk clock index is 0
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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axi_ethernet.tcl: Fix axi_ethernet issue when no sink_pins connected
u-boot dts sync to DTG
Revert "common_proc.tcl: Fix DT-overlay build issue when custom dtsi given"
Revert "device_tree.tcl: Generate the clock nodes at initial"
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Changelog:
(none)
Signed-off-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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zynqmp.dtsi: Update ECAM size to discover up to 256 buses
ddrpsv.tcl: Consider C*DDR_CH*_1 as separate channel
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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device_tree.tcl: Generate the clock nodes at initial
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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The XSCT_STAGING_DIR includes TOPDIR. TOPDIR will change in every users
configuration. We don't care what the XSCT_STAGING_DIR location is, only
that it is set. Thus it is safe to excluse this from the package hash
calculations. This should prevent embeddedsw components from rebuilding
unnecessarily.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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common_proc.tcl: Add psx_acpu_gic support
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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The XSCT_STAGING_DIR includes TOPDIR. TOPDIR will change in every users
configuration. We don't care what the XSCT_STAGING_DIR location is, only
that it is set. Thus it is safe to excluse this from the package hash
calculations. This should prevent embeddedsw components from rebuilding
unnecessarily.
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Add instructions for versal segmented configurations firmware app.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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README instructions had incorrect bbclass, So fix README with right
bbclass.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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device_tree: Add ps_wizard support
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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In Segmented Configuration design _soc.pdi is renamed to _boot.pdi in
xsa and Hence rename _soc.pdi to _boot.pdi in recipe for packaging
Boot.bin.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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mrmac: Fix clocks when misc_clock_3 connected to mrmac s_axi_clk
axi_vdu.tcl: Update vdu dt node as per xlnx, vdu-2.0
rfdc: Add NCO Freq to param list
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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update k24 and kd240 xsa files
Signed-off-by: Manikanta Sreeram <msreeram@xilinx.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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U-boot dts sync
hdmi_rx_ss.mdd: Add "v_hdmi_rxss1" ip support in mdd file
emacps.tcl: Fix device tree compilation issue in Gem based design
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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dp_rx.tcl: Update compatible string for dp_rx
dp_rx:dp_tx: Update dp_rx connected pin name
common_proc.tcl: Add CPM IP status okay
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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axi_can.tcl: Add "xlnx, has-ecc" property in can node only when if ECC enabled in design
axi_mcdma.tcl: Add compatible string "xlnx, eth-dma" for mcdma node
Signed-off-by: Siva Addepalli <siva.addepalli@amd.com>
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Unsetting YAML_DT_BOARD_FLAGS variable will take precedence over
machine conf files during pre-expansion values. Hence remove it.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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device_tree.tcl: Update correct property in opp-table for versal NET
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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common_proc.tcl: Skip updating broad
common_proc.tcl: Clock name fix for dfx_axi_shutdown_manager
common_proc.tcl: Fix Bus node issue with Broadcaster IP
vid_phy_ctrl:hdmi_gt_ctrl: Generate Channels only if connected to DP/HDMI
ispipeline.tcl: Add axis_broadcaster IP support
common_proc.tcl: Add support when axis_broad(NM) connected to isppipeline
mipi_csi2_rx: Use isppipeline_in as remote-endpoint
u-boot sync changes
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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axi_ethernet.tcl: Fix device tree compilation issue in Zynqmp
common_proc.tcl: Add fpga-bridges property to dfx_axi_shutdown_manager
axi_ethernet.tcl: Fix device tree compilation issue in Zynqmp Axi10G DMA, MCDAM & no_1588
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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ptp_1588_timer_syncer.tcl: Update proper compatible string for timer syncer ip
versal:versal-net: Uboot sync changes
mrmac.tcl: Declare fiforx_connect_ip3 variable as empty
Signed-off-by: Siva Addepalli <sivaprasad.addepalli@xilinx.com>
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Since versal dfx full design focused on single xsa
approach, remove static xsa recipe-sysroot.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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xsa recipe-sysroots comments were not clear, Hence update the
comments.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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README.fpgamanager.dtg* md files will be deprecated in upcoming release.
Users should start using README.dfx.dtg.<arch>.<design>.md files for
firmware app instructions.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Inherit dfx_dtg_versal_full.bbclass for Versal full PDI programming
firmware app.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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fpgamanager_dtg_csoc bbclass will be deprecated in upcoming release.
Users should start using dfx_dtg_versal_csoc bbclass for Versal CSoC
DFx Partial firmware app.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Inherit dfx_dtg_versal_csoc.bbclass for Versal CSoC DFx partial firmware
app instead of fpgamanager_dtg_csoc.bbclass as this bbclass will be
deprecated in upcoming release.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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fpgamanager_dtg_dfx bbclass will be deprecated in upcoming release.
Users should start using dfx_dtg_zynqmp/versal_partial bbclass for
ZynqMP or Versal DFx Partial firmware app.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Inherit dfx_dtg_versal_partial.bbclass for Versal DFx partial firmware
app instead of fpgamanager_dtg_dfx.bbclass as this bbclass will be
deprecated in upcoming release.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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Inherit dfx_dtg_zynqmp_partial.bbclass for ZynqMP DFx partial firmware
app instead of fpgamanager_dtg_dfx.bbclass as this bbclass will be
deprecated in upcoming release.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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This is a replica of fpgamanager_dtg_dfx.bbclass for ZynqMP and Versal
DFx partial firmware app. Do not inherit this bbclass directly.
Instead inherit dfx.dtg.<arch>.partial.bbclass.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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fpgamanager_dtg bbclass which will be deprecated in upcoming
release. Users should start using dfx_dtg_zynq/zynqmp_full bbclass for
Zynq-7000 or ZynqMP Full bitstream or dfx_dtg_zynqmp/versal_static
bbclass for ZynqMP or Versa DFx Static firmware app.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@amd.com>
Signed-off-by: Mark Hatle <mark.hatle@amd.com>
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