summaryrefslogtreecommitdiffstats
AgeCommit message (Collapse)Author
2021-02-16librsvg: Update from 2.40.20 to 2.50.1rmacleod/librsvg-broken-wip-2021-02-16Randy MacLeod
The new version is written in Rust. Remove the patches that were backported and drop the reproducibility patch since that code was dropped in the Rust translation. Update the license checksums since the license info was updated to be more consistent in commit: bd8ebc43 Use the LGPL 2.1 consistently Fixes these: https://gitlab.gnome.org/GNOME/librsvg/issues/72 https://gitlab.gnome.org/GNOME/librsvg/issues/432 Also inherit gettext to address: QA Issue: AM_GNU_GETTEXT used but no inherit gettext and sort the inherit list for good measure. Signed-off-by: Randy MacLeod <Randy.MacLeod@windriver.com>
2021-02-16ripgrep: add temporarilyRandy MacLeod
Signed-off-by: Randy MacLeod <Randy.MacLeod@windriver.com>
2021-02-16rust: use nativepython3 rather than host python3Randy MacLeod
Signed-off-by: Randy MacLeod <Randy.MacLeod@windriver.com>
2021-02-16cargo/rust/rustfmt: exclude from worldrmacleod/rust-wip-2021-02-16Randy MacLeod
cargo, rust, and rustfmt can't be built for the targets yet so exclude them from world builds. Signed-off-by: Randy MacLeod <Randy.MacLeod@windriver.com>
2021-02-16Keep only the most recent two Rust versions.Colin Finck
Older ones are already unbuildable and nobody misses them, see https://github.com/meta-rust/meta-rust/issues/298
2021-02-16rust: Drop v8.1a tune for aarch64Alex Kiernan
Building for "+v8.1a" breaks on (at least) Cortex A53 (Armv8-A) on startup with `Illegal instruction`. Fixes: 26609f46d93c ("rust.inc: use 'v8.1a' feature when building for aarch64 instead of 'v8'")
2021-02-16recipes-example/rust-hello-world: move to new url in meta-rust orgCody P Schafer
2021-02-16readme: fix url and link issue numberCody Schafer
2021-02-16rust.inc: use 'v8.1a' feature when building for aarch64 instead of 'v8'Martin Jansa
* get rid of annoying '+v8' is not a recognized feature for this target (ignoring feature) messages in aarch64 builds, they are shown in the log very often: $ grep -c 'is not a recognized feature for this target (ignoring feature)' cargo/1.49.0-r0/temp/log.do_compile.76960 3824 and sometimes the formatting looks strange as well e.g.: | ''+v8' is not a recognized feature for this target (ignoring feature) | +v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | ''+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target (ignoring feature) | (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | ''''''+v8+v8+v8+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target' is not a recognized feature for this target+v8 (ignoring feature) | (ignoring feature) | (ignoring feature) | (ignoring feature) | (ignoring feature) | ' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | '+v8' is not a recognized feature for this target (ignoring feature) | ''+v8+v8' is not a recognized feature for this target' is not a recognized feature for this target (ignoring feature) | (ignoring feature) * not sure when it was changed (if 'v8' ever was valid feature for aarch64) but with 1.49.0 rustc (from gentoo) I see following cpu and feature options for arm and aarch64 (and v8 is listed only for arm, for aarch64 only v8.[123456]a) # rustc --target=arm-unknown-linux-gnueabihf --print target-cpus Available CPUs for this target: arm1020e arm1020t arm1022e arm10e arm10tdmi arm1136j-s arm1136jf-s arm1156t2-s arm1156t2f-s arm1176j-s arm1176jz-s arm1176jzf-s arm710t arm720t arm7tdmi arm7tdmi-s arm8 arm810 arm9 arm920 arm920t arm922t arm926ej-s arm940t arm946e-s arm966e-s arm968e-s arm9e arm9tdmi cortex-a12 cortex-a15 cortex-a17 cortex-a32 cortex-a35 cortex-a5 cortex-a53 cortex-a55 cortex-a57 cortex-a7 cortex-a72 cortex-a73 cortex-a75 cortex-a76 cortex-a76ae cortex-a77 cortex-a78 cortex-a8 cortex-a9 cortex-m0 cortex-m0plus cortex-m1 cortex-m23 cortex-m3 cortex-m33 cortex-m35p cortex-m4 cortex-m55 cortex-m7 cortex-r4 cortex-r4f cortex-r5 cortex-r52 cortex-r7 cortex-r8 cortex-x1 cyclone ep9312 exynos-m3 exynos-m4 exynos-m5 generic iwmmxt krait kryo mpcore mpcorenovfp neoverse-n1 sc000 sc300 strongarm strongarm110 strongarm1100 strongarm1110 swift xscale # rustc --target=aarch64-unknown-linux-gnu --print target-cpus Available CPUs for this target: a64fx apple-a10 apple-a11 apple-a12 apple-a13 apple-a7 apple-a8 apple-a9 apple-latest apple-s4 apple-s5 carmel cortex-a34 cortex-a35 cortex-a53 cortex-a55 cortex-a57 cortex-a65 cortex-a65ae cortex-a72 cortex-a73 cortex-a75 cortex-a76 cortex-a76ae cortex-a77 cortex-a78 cortex-x1 cyclone exynos-m3 exynos-m4 exynos-m5 falkor generic kryo neoverse-e1 neoverse-n1 saphira thunderx thunderx2t99 thunderx3t110 thunderxt81 thunderxt83 thunderxt88 tsv110 # rustc --target=arm-unknown-linux-gnueabihf --print target-features Available features for this target: 32bit - Prefer 32-bit Thumb instrs. 8msecext - Enable support for ARMv8-M Security Extensions. a12 - Cortex-A12 ARM processors. a15 - Cortex-A15 ARM processors. a17 - Cortex-A17 ARM processors. a32 - Cortex-A32 ARM processors. a35 - Cortex-A35 ARM processors. a5 - Cortex-A5 ARM processors. a53 - Cortex-A53 ARM processors. a55 - Cortex-A55 ARM processors. a57 - Cortex-A57 ARM processors. a7 - Cortex-A7 ARM processors. a72 - Cortex-A72 ARM processors. a73 - Cortex-A73 ARM processors. a75 - Cortex-A75 ARM processors. a76 - Cortex-A76 ARM processors. a77 - Cortex-A77 ARM processors. a8 - Cortex-A8 ARM processors. a9 - Cortex-A9 ARM processors. aclass - Is application profile ('A' series). acquire-release - Has v8 acquire/release (lda/ldaex etc) instructions. aes - Enable AES support. armv2 - ARMv2 architecture. armv2a - ARMv2a architecture. armv3 - ARMv3 architecture. armv3m - ARMv3m architecture. armv4 - ARMv4 architecture. armv4t - ARMv4t architecture. armv5t - ARMv5t architecture. armv5te - ARMv5te architecture. armv5tej - ARMv5tej architecture. armv6 - ARMv6 architecture. armv6-m - ARMv6m architecture. armv6j - ARMv7a architecture. armv6k - ARMv6k architecture. armv6kz - ARMv6kz architecture. armv6s-m - ARMv6sm architecture. armv6t2 - ARMv6t2 architecture. armv7-a - ARMv7a architecture. armv7-m - ARMv7m architecture. armv7-r - ARMv7r architecture. armv7e-m - ARMv7em architecture. armv7k - ARMv7a architecture. armv7s - ARMv7a architecture. armv7ve - ARMv7ve architecture. armv8-a - ARMv8a architecture. armv8-m.base - ARMv8mBaseline architecture. armv8-m.main - ARMv8mMainline architecture. armv8-r - ARMv8r architecture. armv8.1-a - ARMv81a architecture. armv8.1-m.main - ARMv81mMainline architecture. armv8.2-a - ARMv82a architecture. armv8.3-a - ARMv83a architecture. armv8.4-a - ARMv84a architecture. armv8.5-a - ARMv85a architecture. armv8.6-a - ARMv86a architecture. avoid-movs-shop - Avoid movs instructions with shifter operand. avoid-partial-cpsr - Avoid CPSR partial update for OOO execution. bf16 - Enable support for BFloat16 instructions. cde - Support CDE instructions. cdecp0 - Coprocessor 0 ISA is CDEv1. cdecp1 - Coprocessor 1 ISA is CDEv1. cdecp2 - Coprocessor 2 ISA is CDEv1. cdecp3 - Coprocessor 3 ISA is CDEv1. cdecp4 - Coprocessor 4 ISA is CDEv1. cdecp5 - Coprocessor 5 ISA is CDEv1. cdecp6 - Coprocessor 6 ISA is CDEv1. cdecp7 - Coprocessor 7 ISA is CDEv1. cheap-predicable-cpsr - Disable +1 predication cost for instructions updating CPSR. cortex-a78 - Cortex-A78 ARM processors. cortex-x1 - Cortex-X1 ARM processors. crc - Enable support for CRC instructions. crypto - Enable support for Cryptography extensions. d32 - Extend FP to 32 double registers. db - Has data barrier (dmb/dsb) instructions. dfb - Has full data barrier (dfb) instruction. disable-postra-scheduler - Don't schedule again after register allocation. dont-widen-vmovs - Don't widen VMOVS to VMOVD. dotprod - Enable support for dot product instructions. dsp - Supports DSP instructions in ARM and/or Thumb2. execute-only - Enable the generation of execute only code.. expand-fp-mlx - Expand VFP/NEON MLA/MLS instructions. exynos - Samsung Exynos processors. fp-armv8 - Enable ARMv8 FP. fp-armv8d16 - Enable ARMv8 FP with only 16 d-registers. fp-armv8d16sp - Enable ARMv8 FP with only 16 d-registers and no double precision. fp-armv8sp - Enable ARMv8 FP with no double precision. fp16 - Enable half-precision floating point. fp16fml - Enable full half-precision floating point fml instructions. fp64 - Floating point unit supports double precision. fpao - Enable fast computation of positive address offsets. fpregs - Enable FP registers. fpregs16 - Enable 16-bit FP registers. fpregs64 - Enable 64-bit FP registers. fullfp16 - Enable full half-precision floating point. fuse-aes - CPU fuses AES crypto operations. fuse-literals - CPU fuses literal generation operations. hwdiv - Enable divide instructions in Thumb. hwdiv-arm - Enable divide instructions in ARM mode. i8mm - Enable Matrix Multiply Int8 Extension. iwmmxt - ARMv5te architecture. iwmmxt2 - ARMv5te architecture. krait - Qualcomm Krait processors. kryo - Qualcomm Kryo processors. lob - Enable Low Overhead Branch extensions. long-calls - Generate calls via indirect call instructions. loop-align - Prefer 32-bit alignment for loops. m3 - Cortex-M3 ARM processors. mclass - Is microcontroller profile ('M' series). mp - Supports Multiprocessing extension. muxed-units - Has muxed AGU and NEON/FPU. mve - Support M-Class Vector Extension with integer ops. mve.fp - Support M-Class Vector Extension with integer and floating ops. mve1beat - Model MVE instructions as a 1 beat per tick architecture. mve2beat - Model MVE instructions as a 2 beats per tick architecture. mve4beat - Model MVE instructions as a 4 beats per tick architecture. nacl-trap - NaCl trap. neon - Enable NEON instructions. neon-fpmovs - Convert VMOVSR, VMOVRS, VMOVS to NEON. neonfp - Use NEON for single precision FP. no-branch-predictor - Has no branch predictor. no-movt - Don't use movt/movw pairs for 32-bit imms. no-neg-immediates - Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.. noarm - Does not support ARM mode execution. nonpipelined-vfp - VFP instructions are not pipelined. perfmon - Enable support for Performance Monitor extensions. prefer-ishst - Prefer ISHST barriers. prefer-vmovsr - Prefer VMOVSR. prof-unpr - Is profitable to unpredicate. r4 - Cortex-R4 ARM processors. r5 - Cortex-R5 ARM processors. r52 - Cortex-R52 ARM processors. r7 - Cortex-R7 ARM processors. ras - Enable Reliability, Availability and Serviceability extensions. rclass - Is realtime profile ('R' series). read-tp-hard - Reading thread pointer from register. reserve-r9 - Reserve R9, making it unavailable as GPR. ret-addr-stack - Has return address stack. sb - Enable v8.5a Speculation Barrier. sha2 - Enable SHA1 and SHA256 support. slow-fp-brcc - FP compare + branch is slow. slow-load-D-subreg - Loading into D subregs is slow. slow-odd-reg - VLDM/VSTM starting with an odd register is slow. slow-vdup32 - Has slow VDUP32 - prefer VMOV. slow-vgetlni32 - Has slow VGETLNi32 - prefer VMOV. slowfpvfmx - Disable VFP / NEON FMA instructions. slowfpvmlx - Disable VFP / NEON MAC instructions. soft-float - Use software floating point features.. splat-vfp-neon - Splat register from VFP to NEON. strict-align - Disallow all unaligned memory access. swift - Swift ARM processors. thumb-mode - Thumb mode. thumb2 - Enable Thumb2 instructions. trustzone - Enable support for TrustZone security extensions. use-misched - Use the MachineScheduler. v4t - Support ARM v4T instructions. v5t - Support ARM v5T instructions. v5te - Support ARM v5TE, v5TEj, and v5TExp instructions. v6 - Support ARM v6 instructions. v6k - Support ARM v6k instructions. v6m - Support ARM v6M instructions. v6t2 - Support ARM v6t2 instructions. v7 - Support ARM v7 instructions. v7clrex - Has v7 clrex instruction. v8 - Support ARM v8 instructions. v8.1a - Support ARM v8.1a instructions. v8.1m.main - Support ARM v8-1M Mainline instructions. v8.2a - Support ARM v8.2a instructions. v8.3a - Support ARM v8.3a instructions. v8.4a - Support ARM v8.4a instructions. v8.5a - Support ARM v8.5a instructions. v8.6a - Support ARM v8.6a instructions. v8m - Support ARM v8M Baseline instructions. v8m.main - Support ARM v8M Mainline instructions. vfp2 - Enable VFP2 instructions. vfp2sp - Enable VFP2 instructions with no double precision. vfp3 - Enable VFP3 instructions. vfp3d16 - Enable VFP3 instructions with only 16 d-registers. vfp3d16sp - Enable VFP3 instructions with only 16 d-registers and no double precision. vfp3sp - Enable VFP3 instructions with no double precision. vfp4 - Enable VFP4 instructions. vfp4d16 - Enable VFP4 instructions with only 16 d-registers. vfp4d16sp - Enable VFP4 instructions with only 16 d-registers and no double precision. vfp4sp - Enable VFP4 instructions with no double precision. virtualization - Supports Virtualization extension. vldn-align - Check for VLDn unaligned access. vmlx-forwarding - Has multiplier accumulator forwarding. vmlx-hazards - Has VMLx hazards. wide-stride-vfp - Use a wide stride when allocating VFP registers. xscale - ARMv5te architecture. zcz - Has zero-cycle zeroing instructions. Rust-specific features: crt-static - Enables libraries with C Run-time Libraries(CRT) to be statically linked. Use +feature to enable a feature, or -feature to disable it. For example, rustc -C -target-cpu=mycpu -C target-feature=+feature1,-feature2 # rustc --target=aarch64-unknown-linux-gnu --print target-features Available features for this target: a35 - Cortex-A35 ARM processors. a53 - Cortex-A53 ARM processors. a55 - Cortex-A55 ARM processors. a57 - Cortex-A57 ARM processors. a64fx - Fujitsu A64FX processors. a65 - Cortex-A65 ARM processors. a72 - Cortex-A72 ARM processors. a73 - Cortex-A73 ARM processors. a75 - Cortex-A75 ARM processors. a76 - Cortex-A76 ARM processors. a77 - Cortex-A77 ARM processors. aes - Enable AES support. aggressive-fma - Enable Aggressive FMA for floating-point.. alternate-sextload-cvt-f32-pattern - Use alternative pattern for sextload convert to f32. altnzcv - Enable alternative NZCV format for floating point comparisons. am - Enable v8.4-A Activity Monitors extension. amvs - Enable v8.6-A Activity Monitors Virtualization support. apple-a10 - Apple A10. apple-a11 - Apple A11. apple-a12 - Apple A12. apple-a13 - Apple A13. apple-a7 - Apple A7 (the CPU formerly known as Cyclone). arith-bcc-fusion - CPU fuses arithmetic+bcc operations. arith-cbz-fusion - CPU fuses arithmetic + cbz/cbnz operations. balance-fp-ops - balance mix of odd and even D-registers for fp multiply(-accumulate) ops. bf16 - Enable BFloat16 Extension. bti - Enable Branch Target Identification. call-saved-x10 - Make X10 callee saved.. call-saved-x11 - Make X11 callee saved.. call-saved-x12 - Make X12 callee saved.. call-saved-x13 - Make X13 callee saved.. call-saved-x14 - Make X14 callee saved.. call-saved-x15 - Make X15 callee saved.. call-saved-x18 - Make X18 callee saved.. call-saved-x8 - Make X8 callee saved.. call-saved-x9 - Make X9 callee saved.. carmel - Nvidia Carmel processors. ccdp - Enable v8.5 Cache Clean to Point of Deep Persistence. ccidx - Enable v8.3-A Extend of the CCSIDR number of sets. ccpp - Enable v8.2 data Cache Clean to Point of Persistence. complxnum - Enable v8.3-A Floating-point complex number support. cortex-a78 - Cortex-A78 ARM processors. cortex-x1 - Cortex-X1 ARM processors. crc - Enable ARMv8 CRC-32 checksum instructions. crypto - Enable cryptographic instructions. custom-cheap-as-move - Use custom handling of cheap instructions. disable-latency-sched-heuristic - Disable latency scheduling heuristic. dit - Enable v8.4-A Data Independent Timing instructions. dotprod - Enable dot product support. ecv - Enable enhanced counter virtualization extension. ete - Enable Embedded Trace Extension. exynos-cheap-as-move - Use Exynos specific handling of cheap instructions. exynosm3 - Samsung Exynos-M3 processors. exynosm4 - Samsung Exynos-M4 processors. f32mm - Enable Matrix Multiply FP32 Extension. f64mm - Enable Matrix Multiply FP64 Extension. falkor - Qualcomm Falkor processors. fgt - Enable fine grained virtualization traps extension. fmi - Enable v8.4-A Flag Manipulation Instructions. force-32bit-jump-tables - Force jump table entries to be 32-bits wide except at MinSize. fp-armv8 - Enable ARMv8 FP. fp16fml - Enable FP16 FML instructions. fptoint - Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int. fullfp16 - Full FP16. fuse-address - CPU fuses address generation and memory operations. fuse-aes - CPU fuses AES crypto operations. fuse-arith-logic - CPU fuses arithmetic and logic operations. fuse-crypto-eor - CPU fuses AES/PMULL and EOR operations. fuse-csel - CPU fuses conditional select operations. fuse-literals - CPU fuses literal generation operations. harden-sls-blr - Harden against straight line speculation across BLR instructions. harden-sls-retbr - Harden against straight line speculation across RET and BR instructions. i8mm - Enable Matrix Multiply Int8 Extension. jsconv - Enable v8.3-A JavaScript FP conversion instructions. kryo - Qualcomm Kryo processors. lor - Enables ARM v8.1 Limited Ordering Regions extension. lse - Enable ARMv8.1 Large System Extension (LSE) atomic instructions. lsl-fast - CPU has a fastpath logical shift of up to 3 places. mpam - Enable v8.4-A Memory system Partitioning and Monitoring extension. mte - Enable Memory Tagging Extension. neon - Enable Advanced SIMD instructions. neoversee1 - Neoverse E1 ARM processors. neoversen1 - Neoverse N1 ARM processors. no-neg-immediates - Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.. nv - Enable v8.4-A Nested Virtualization Enchancement. pa - Enable v8.3-A Pointer Authentication extension. pan - Enables ARM v8.1 Privileged Access-Never extension. pan-rwv - Enable v8.2 PAN s1e1R and s1e1W Variants. perfmon - Enable ARMv8 PMUv3 Performance Monitors extension. pmu - Enable v8.4-A PMU extension. predictable-select-expensive - Prefer likely predicted branches over selects. predres - Enable v8.5a execution and data prediction invalidation instructions. rand - Enable Random Number generation instructions. ras - Enable ARMv8 Reliability, Availability and Serviceability Extensions. rasv8_4 - Enable v8.4-A Reliability, Availability and Serviceability extension. rcpc - Enable support for RCPC extension. rcpc-immo - Enable v8.4-A RCPC instructions with Immediate Offsets. rdm - Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions. reserve-x1 - Reserve X1, making it unavailable as a GPR. reserve-x10 - Reserve X10, making it unavailable as a GPR. reserve-x11 - Reserve X11, making it unavailable as a GPR. reserve-x12 - Reserve X12, making it unavailable as a GPR. reserve-x13 - Reserve X13, making it unavailable as a GPR. reserve-x14 - Reserve X14, making it unavailable as a GPR. reserve-x15 - Reserve X15, making it unavailable as a GPR. reserve-x18 - Reserve X18, making it unavailable as a GPR. reserve-x2 - Reserve X2, making it unavailable as a GPR. reserve-x20 - Reserve X20, making it unavailable as a GPR. reserve-x21 - Reserve X21, making it unavailable as a GPR. reserve-x22 - Reserve X22, making it unavailable as a GPR. reserve-x23 - Reserve X23, making it unavailable as a GPR. reserve-x24 - Reserve X24, making it unavailable as a GPR. reserve-x25 - Reserve X25, making it unavailable as a GPR. reserve-x26 - Reserve X26, making it unavailable as a GPR. reserve-x27 - Reserve X27, making it unavailable as a GPR. reserve-x28 - Reserve X28, making it unavailable as a GPR. reserve-x3 - Reserve X3, making it unavailable as a GPR. reserve-x30 - Reserve X30, making it unavailable as a GPR. reserve-x4 - Reserve X4, making it unavailable as a GPR. reserve-x5 - Reserve X5, making it unavailable as a GPR. reserve-x6 - Reserve X6, making it unavailable as a GPR. reserve-x7 - Reserve X7, making it unavailable as a GPR. reserve-x9 - Reserve X9, making it unavailable as a GPR. saphira - Qualcomm Saphira processors. sb - Enable v8.5 Speculation Barrier. sel2 - Enable v8.4-A Secure Exception Level 2 extension. sha2 - Enable SHA1 and SHA256 support. sha3 - Enable SHA512 and SHA3 support. slow-misaligned-128store - Misaligned 128 bit stores are slow. slow-paired-128 - Paired 128 bit loads and stores are slow. slow-strqro-store - STR of Q register with register offset is slow. sm4 - Enable SM3 and SM4 support. spe - Enable Statistical Profiling extension. specrestrict - Enable architectural speculation restriction. ssbs - Enable Speculative Store Bypass Safe bit. strict-align - Disallow all unaligned memory access. sve - Enable Scalable Vector Extension (SVE) instructions. sve2 - Enable Scalable Vector Extension 2 (SVE2) instructions. sve2-aes - Enable AES SVE2 instructions. sve2-bitperm - Enable bit permutation SVE2 instructions. sve2-sha3 - Enable SHA3 SVE2 instructions. sve2-sm4 - Enable SM4 SVE2 instructions. tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits. thunderx - Cavium ThunderX processors. thunderx2t99 - Cavium ThunderX2 processors. thunderx3t110 - Marvell ThunderX3 processors. thunderxt81 - Cavium ThunderX processors. thunderxt83 - Cavium ThunderX processors. thunderxt88 - Cavium ThunderX processors. tlb-rmi - Enable v8.4-A TLB Range and Maintenance Instructions. tme - Enable Transactional Memory Extension. tpidr-el1 - Permit use of TPIDR_EL1 for the TLS base. tpidr-el2 - Permit use of TPIDR_EL2 for the TLS base. tpidr-el3 - Permit use of TPIDR_EL3 for the TLS base. tracev8.4 - Enable v8.4-A Trace extension. trbe - Enable Trace Buffer Extension. tsv110 - HiSilicon TS-V110 processors. uaops - Enable v8.2 UAO PState. use-aa - Use alias analysis during codegen. use-experimental-zeroing-pseudos - Hint to the compiler that the MOVPRFX instruction is merged with destructive operations. use-postra-scheduler - Schedule again after register allocation. use-reciprocal-square-root - Use the reciprocal square root approximation. v8.1a - Support ARM v8.1a instructions. v8.2a - Support ARM v8.2a instructions. v8.3a - Support ARM v8.3a instructions. v8.4a - Support ARM v8.4a instructions. v8.5a - Support ARM v8.5a instructions. v8.6a - Support ARM v8.6a instructions. vh - Enables ARM v8.1 Virtual Host extension. zcm - Has zero-cycle register moves. zcz - Has zero-cycle zeroing instructions. zcz-fp - Has zero-cycle zeroing instructions for FP registers. zcz-fp-workaround - The zero-cycle floating-point zeroing instruction has a bug. zcz-gp - Has zero-cycle zeroing instructions for generic registers. Rust-specific features: crt-static - Enables libraries with C Run-time Libraries(CRT) to be statically linked. Use +feature to enable a feature, or -feature to disable it. For example, rustc -C -target-cpu=mycpu -C target-feature=+feature1,-feature2 Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust_versions.inc: switch the default version to 1.49.0Martin Jansa
Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16{cargo,rust}-1.49.0: simplify as in ↵Martin Jansa
https://github.com/meta-rust/meta-rust/pull/299 Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16Fix *-native cargo buildsJohan Anderholm
Normally all *-native packages needs to depend on cargo-native in order to be able to use cargo. When building cargo-native however, this is not available and we use a snapshot. Fixes #302.
2021-02-16rust-source, rust-snaphost: drop md5sumsMartin Jansa
* for consistency as 1.43.0 and 1.47.0 already use only sha256sum Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust-source, rust-snapshot: simplify as wellMartin Jansa
* move common stuff from rust-source to rust.inc and from rust-snapshot to rust-target.inc * 1.34.2 checksums were changed because unified SRC_URI is using tar.xz for this version as well (instead of tar.gz used before here) Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16add rust 1.49.0Dan Callaghan
Now it seems `./x.py install` is the only way to assemble a fully working stage 2 cross-built compiler. See rust-lang/rust#81702.
2021-02-16rust-target.inc: add new include file to simplify all rust_*.bbMartin Jansa
Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust_versions.inc: add include for easy switching between versionsMartin Jansa
Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16cargo: move LIC_FILES_CHKSUM from cargo_*.bb to cargo.inc where LICENSE is setMartin Jansa
* only the oldest 1.34.2 is the exception with different value, so stop duplicating it Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust: move LIC_FILES_CHKSUM from rust-source-*.inc to rust.inc where LICENSE ↵Martin Jansa
is set Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust-llvm-ncsa.inc: reorder to actually set LICENSE and LIC_FILES_CHKSUMMartin Jansa
* rust-llvm.inc sets LICENSE and corresponding LIC_FILES_CHKSUM for Apache-2.0-with-LLVM-exception, but the recipes which include rust-llvm-ncsa.inc need to change it to NCSA. Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16Revert "rust-llvm: Use early variable assignment for the license checksum in ↵Martin Jansa
rust-llvm.inc" This reverts commit 5dda6c427a7cca264870f6b7fc64753203e7d30d. This breaks rust-llvm builds with: ERROR: QA Issue: rust-llvm-native: LIC_FILES_CHKSUM points to an invalid file: TOPDIR/BUILD/work/x86_64-linux/rust-llvm-native/1.47.0-r0/rustc-1.47.0-src/src/llvm-project/llvm/COPYRIGHT [license-checksum] Signed-off-by: Martin Jansa <Martin.Jansa@gmail.com>
2021-02-16rust-hello-world: enable LTO in the buildDan Callaghan
If the libstd-rs recipe is not correctly embedding LVM bitcode in its output, then it can produce a toolchain that appears to work until you try building a project that requests LTO: error: failed to get bitcode from object file for LTO (Bitcode section not found in object file) Enable LTO for rust-hello-world to give us an easy watch to catch such problems.
2021-02-16libstd-rs: embed bitcode for LTODan Callaghan
Fixes #294.
2021-02-16cargo: Mark the cargo-native dependency specific to targetKhem Raj
Fixes dependency loop These are usually caused by circular dependencies and any circular dependency chains found will be printed below. Increase the debug level to see a list of unbuildable tasks. Identifying dependency loops (this may take a short while)... ERROR: Dependency loop #1 found: Task virtual:native:/mnt/b/yoe/master/sources/meta-rust/recipes-devtools/cargo/cargo_1.47.0.bb:do_compile (dependent Tasks ['cargo_1.47.0.bb:do_configure']) Task virtual:native:/mnt/b/yoe/master/sources/meta-rust/recipes-devtools/cargo/cargo_1.47.0.bb:do_install (dependent Tasks ['cargo_1.47.0.bb:do_compile']) Task virtual:native:/mnt/b/yoe/master/sources/meta-rust/recipes-devtools/cargo/cargo_1.47.0.bb:do_populate_sysroot (dependent Tasks ['cargo_1.47.0.bb:do_install']) Task virtual:native:/mnt/b/yoe/master/sources/meta-rust/recipes-devtools/cargo/cargo_1.47.0.bb:do_prepare_recipe_sysroot (dependent Tasks ['cargo_1.47.0.bb:do_populate_sysroot', 'openssl_1.1.1i.bb:do_populate_sysroot', 'curl_7.74.0.bb:do_populate_sysroot', 'rust_1.47.0.bb:do_populate_sysroot', 'zlib_1.2.11.bb:do_populate_sysroot', 'ca-certificates_20210119.bb:do_populate_sysroot', 'libssh2_1.9.0.bb:do_populate_sysroot', 'cargo_1.47.0.bb:do_fetch']) Task virtual:native:/mnt/b/yoe/master/sources/meta-rust/recipes-devtools/cargo/cargo_1.47.0.bb:do_configure (dependent Tasks ['cargo_1.47.0.bb:do_prepare_recipe_sysroot', 'cargo_1.47.0.bb:do_patch', 'cargo_1.47.0.bb:do_rust_create_wrappers', 'cargo_1.47.0.bb:do_cargo_setup_snapshot']) ERROR: Command execution failed: 1 Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16rust-llvm: Use early variable assignment for the license checksum in ↵Florin Sarbu
rust-llvm.inc Because rust-llvm-ncsa.inc requires rust-llvm.inc we do not want that the latter overrides the license checksum set in the former. Signed-off-by: Florin Sarbu <florin@balena.io>
2021-02-16libssh2: Fix build with autoconf 2.70+Khem Raj
Fixes configure.ac:130: error: m4_undefine: undefined macro: backend Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: upgrade 1.0.0 -> 1.0.1Andreas Müller
Signed-off-by: Andreas Müller <schnitzeltony@gmail.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: Enable pcre2 regexp backendKhem Raj
As a side effect it helps the builds where pcre is staged in native sysroot and CMake system is confusing that and adds it to linker cmdline, its evident with clang as cross compiler since it brings libpcre-native into native sysroot Signed-off-by: Khem Raj <raj.khem@gmail.com> Cc: Alistair Francis <alistair@alistair23.me>
2021-02-16libgit2: Update to v1.0.0Alistair Francis
Signed-off-by: Alistair Francis <alistair@alistair23.me> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: Upgrade to 0.28.4Khem Raj
Fix library install path to consider multilib as well Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: Don't pass parameters with their default values to cmakeAdrian Bunk
Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: Upgrade 0.27.9 -> 0.28.3Adrian Bunk
Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libgit2: Upgrade 0.27.8 -> 0.27.9Adrian Bunk
This is a security release on the 0.27 branch. Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: enhance ptestChangqing Li
support testcase ssh2.sh Signed-off-by: Changqing Li <changqing.li@windriver.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: fix ptestSakib Sajal
One of the ptest was failing as it was missing an RDEPENDS for its test on documentation. Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: enable ptestSakib Sajal
Signed-off-by: Sakib Sajal <sakib.sajal@windriver.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: add nativesdk supportPierre-Jean Texier
Fixes: Missing or unbuildable dependency chain was: ['nativesdk-cmake', 'nativesdk-curl', 'nativesdk-libssh2'] So, extend libssh2 to nativesdk to fix this issue. Signed-off-by: Pierre-Jean Texier <pjtexier@koncepto.io> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: Security Advisory - libssh2 - CVE-2019-17498Li Zhou
Porting the patch from <https://github.com/libssh2/libssh2/commit/ dedcbd106f8e52d5586b0205bc7677e4c9868f9c> to solve CVE-2019-17498. Signed-off-by: Li Zhou <li.zhou@windriver.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: upgrade 1.8.2 -> 1.9.0Zheng Ruoqin
1) Upgrade libssh2 from 1.8.2 to 1.9.0. 2) Modify PACKAGECONFIG for configure options have been changed in new version. Signed-off-by: Zheng Ruoqin <zhengrq.fnst@cn.fujitsu.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libssh2: Clarify BSD license variantChristophe PRIOUZEAU
The License of of libssh2 is BSD-3-Clause. Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com> Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16libstd-rs: Remove libunwind on riscvKhem Raj
riscv port of libunwind is not available yet Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16rust: Add riscv32/riscv64 supportKhem Raj
Set the cpu, features, and abi correctly Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16rust: Build rust backendKhem Raj
In llvm11 we have both riscv32 or riscv64 backends so enable them Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16rust: Correct the data layout for riscv32Khem Raj
This now matches with llvm target backend in llvm 11 Signed-off-by: Khem Raj <raj.khem@gmail.com>
2021-02-16cargo_common: Make output more readableJohan Anderholm
2021-02-16cargo: Enable build separationJohan Anderholm
Place generated artifacts in the directory suggested by bitbake (${B}) instead of directly in the source directory. This has multiple advantages such as the ability to share source directory between multiple machine types without risking cross contamination.
2021-02-16Use proper llvm-target for armv7Johan Anderholm
arm-unknown-linux-gnueabihf was incorrectly used as llvm-target instead of armv7-unknown-linux-gnueabihf when building for some Cortex A SoCs. This may cause segfaults in non trivial rust applications on ARMv7 when e.g. +a7 is passed to LLVM. It seems to differ between different versions of the compiler and LLVM versions.
2021-02-16add rust 1.47.0Dan Callaghan
2021-02-16clean up some common definitions across rust versionsDan Callaghan
These bits and pieces had evidently been copy-pasted forward into each new recipe version, but now they are all identical and can be tidied up.
2021-02-16rust-bin.bbclass: Do not use append and += togetherKhem Raj
this is undefined behavior in bitbake, prepend space instead Signed-off-by: Khem Raj <raj.khem@gmail.com>
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-20 05:34:10 +0000