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From: Andre Przywara <andre.przywara@arm.com>
To: linux-eng@arm.com
Cc: Ross Burton <ross.burton@arm.com>,
Robin Murphy <robin.murphy@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>
Subject: [PATCH] clocksource/drivers/arm_arch_timer: limit XGene-1 workaround
Date: Fri, 13 Oct 2023 16:38:55 +0100
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MIME-Version: 1.0
The AppliedMicro XGene-1 CPU has an erratum where the timer condition
would only consider TVAL, not CVAL. We currently apply a workaround when
seeing the PARTNUM field of MIDR_EL1 being 0x000, under the assumption
that this would match only the XGene-1 CPU model.
However even XGene-3 (aka Ampere eMAG) uses that same part number, and
only differs in the "revision" field: XGene-1's MIDR is 0x500f0000, the
eMAG reports 0x503f0002. Experiments show the latter doesn't show the
faulty behaviour.
Increase the specificity of the check to only consider partnum 0x000 and
revision 0x00, to exclude the Ampere eMAG.
We keep the old definition of APM_CPU_PART_POTENZA, since this is used
in KVM, too, and it's some kind of ABI there.
Fixes: 012f18850452 ("clocksource/drivers/arm_arch_timer: Work around broken CVAL implementations")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Upstream-Status: Submitted
Signed-off-by: Ross Burton <ross.burton@arm.com>
---
Hi,
Ross, Robin, can you give this a spin on your eMAG boxes, to see if the
message ("Broken CNTx_CVAL_EL1, using 31 bit TVAL instead.") disappears?
And confirm that the box still works?
Also appreciate any feedback about the wording of the commit message and
the naming of the symbols.
Cheers,
Andre
arch/arm64/include/asm/cputype.h | 2 ++
drivers/clocksource/arm_arch_timer.c | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 74d00feb62f03..225ba48e00e7e 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -87,6 +87,8 @@
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
#define APM_CPU_PART_POTENZA 0x000
+#define APM_CPU_PART_XGENE 0x000
+#define APM_CPU_VAR_POTENZA 0x00
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 7dd2c615bce23..071b04f1ee730 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -836,8 +836,9 @@ static u64 __arch_timer_check_delta(void)
* Note that TVAL is signed, thus has only 31 of its
* 32 bits to express magnitude.
*/
- MIDR_ALL_VERSIONS(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
- APM_CPU_PART_POTENZA)),
+ MIDR_REV_RANGE(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
+ APM_CPU_PART_XGENE),
+ APM_CPU_VAR_POTENZA, 0x0, 0xf),
{},
};
--
2.25.1
|
